This invention relates to analog-to-digital converters and, more particularly, to the sampling mechanism for the front-end of a converter, particularly a converter using a pipelined architecture and which is preferably implemented in CMOS technology.
Analog-to-digital converters (also called A/D converters or ADCs) are ubiquitous building blocks of electronic systems which process physical signals from transducers or electronic signal generating circuits. Among the many applications which employ ADC""s are applications such as wireless receivers and ultrasound systems, wire line interfaces, cameras and camcorders, all of which make use of ADC""s having typically about 10-bit resolution and sampling rates at around 40 MHz. Most of them require low power consumption as well as low noise, and many of them require high dynamic performance using Nyquist or higher input frequencies. Modem CMOS technology provides the opportunity for implementing medium resolution (i.e., about 8-12 bit) ADC""s that are able to fulfill the requirements of such applications. However, achieving good dynamic performance for high input frequencies has proved to be a difficult task. Nyquist rate ADC""s that operate at high frequencies with reasonable power consumption have mainly been implemented using BiCMOS technology and only recently are becoming accessible in CMOS. A need exists, therefore, for an ADC of such resolution that features low power consumption combined with good dynamic performance.
For applications such as those identified above, the list of design requirements for an ADC is topped by a low power Nyquist rate (and above) implementation suitable for CMOS fabrication. Also, there is a need to preserve good linearity and low noise such that the converter exhibits substantially full resolution for input frequencies well beyond Nyquist. A specific challenge is provided by virtue of the aforementioned requirements often conflicting. For example, low power conflicts with high speed operation.
There are quite a few architectures which could be used to implement high-resolution (i.e., 10-bit or greater) ADC. However, straight flash topologies are impractical from a power (as well as area) perspective. Also, successive approximation (or cyclic) topologies are not practical for high speed Nyquist rate operation. Folding and/or interpolating (averaging) topologies have been successfully used. They exhibit low power due mostly to interpolation, and low latency (i.e., delay from input to the output); however, they do not excel regarding dynamic performance and are more suited to bipolar than to CMOS implementations. Pipeline architectures are known to use less power than the other named architectures, but at the expense of conversion latency. In pipeline converters, power consumption can be optimized by an appropriate selection of bits per stage and capacitor scaling down the pipeline. Also, pipeline architectures are successfully implemented in CMOS using switched capacitor designs which make them easy to integrate. Speed can be improved through the use of various parallel blocks through the pipeline, although usually at the expense of higher power consumption and less impressive dynamic performance for high input frequencies.
Turning to FIG. 1, there is depicted a block diagram for a first typical architecture for a residue stage of a typical prior art pipelined ADC 10. An input signal Vin is applied at input node 12. Within the stage, this node is connected to the input of a quantizer 14 and a (usually switched-capacitor) residue generator 16. The quantizer is typically an analog-to-digital converter such as a flash converter. The output of the quantizer 14 is a digital representation of the input signal, usually of only a few bits resolution. A DAC 18 in the residue stage generates a corresponding analog signal representing the quantizer output, and supplies this analog signal to a summer 22. At substantially the same time as the quantizer samples the analog input signal in response to a clock signal applied at 24, a sample-and-hold (S/H) circuit 26 acquires and holds a sample of the input signal and supplies that held value to the summer 22. Summer 22 forms a difference signal representing the difference between the sampled input signal from the S/H circuit and the approximated input signal reproduction at the output of DAC 18. The resulting difference, or error, signal at 28 is preferably amplified by an amplifier 30 to scale the output residue signal at 32 to take advantage of the dynamic range of the next stage in the pipeline.
The accuracy of the residue generation (and, thus, the whole converter) is highly dependent, of course, on the S/H circuit and the quantizer sampling the input signal at the same time. If there is too large a difference in the timing of those samples, then the residue signal ceases to represent the difference between the input signal at an instant and the ability of the quantizer and DAC to reproduce that input signal value. Hence the next stage will be presented with an error signal beyond its range of ability to correct for the initial conversion inaccuracy.
Due to that problem, or limitation on performance, in order to capture high-frequency input signals, most converters, including pipeline ADC""s, make use of a front-end S/H circuit, as shown in FIG. 2. There, a S/H circuit 34 has been added between the input signal and node 12. S/H circuit 34 is clocked (i.e., takes its sample) half a clock cycle from S/H circuit 26 and quantizer 14. With this arrangement, input to the node 12 is not moving when it is sampled, so there is no risk that the quantizer and residue stage will sample different values of the waveform. However, S/H circuit 34 requires significant power. Also, inasmuch as the output of the S/H circuit 34 is what is sampled by the quantizer, the S/H circuit 34 may be viewed as a potentially significant source of input-referred noise which can be amplified by, and limit the noise performance of, the whole converter. FIG. 3A presents such a typical prior art S/H circuit, the switches of which are operated by the control signals shown in FIG. 3B, the individual control signal which operates a switch being labeled next to the switch and a switch being closed when its control signal is asserted as a logical high value. Initially, at a time T1, switches 42p, 42n, 46, 48p and 48n are closed and switch 44 is open. This is know as the track phase. The input voltage (shown here as a differential input Vinpxe2x88x92Vinn) is sampled on capacitors Cinp and Cinn at the end of the tracking phase at T2 (i.e., when "PHgr"1p and then "PHgr"1 is de-asserted). During the hold phase which occurs next (with "PHgr"1 de-asserted and "PHgr"2 asserted), switches 42p, 42n, 46, 48p and 48n are open, switches 44, 52p and 52n are closed and the charge from the sampling capacitors Cinp and Cinn is transferred to corresponding feedback capacitors Cfp and Cfn from capacitors Cinp and Cinn such that each of the output voltages is a scaled copy of the corresponding sampled input voltage. Note that this circuit can accommodate single-ended inputs, too, or, in general, a large input comrnmon-mode range, as opposed to the xe2x80x9cflip-aroundxe2x80x9d type of SHA such as that shown in S. Sutarja and P. R. Gray, xe2x80x9cA pipelined 13-bit, 250-ks/s, 5V analog-to-digital converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. 23, no. 5, pp 1316-1323, December 1988. Also, this circuit can provide voltage gain.
The above-identified and other needs are met according to the present invention, by a converter architecture which avoids the use of a dedicated input sample-and-hold amplifier (SHA) (or sample-and-hold circuit or network, those terms being used interchangeably herein) by distributing the sampling operation such that it resides in both a quantizer and a residue generator. The residue generator and the quantizer sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. The degree of matching of the sampling characteristics depends on the expected frequency of the input voltage. For a greater input voltage frequency, the degree of matching required is higher.
Such a quantizer may, for example, employ either a single SHA and ADC or in the event the ADC is a flash converter, instead of a single SHA there may be provided one S/H circuit associated with each comparator in the flash converter.
This architecture may be used stand-alone or as a first stage of a pipeline converter. That stage (and all subsequent stages except for the last stage) includes, in one embodiment, both a quantizer and a residue generator.
One embodiment of the invention thus is directed to a pipeline converter with a low-power ADC front-end circuit that does not require a dedicated sample-and-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one corresponding to a residue generator, and the other directed to a flash comparator (the quantizer), inside of the first stage of the converter.
The lack of a dedicated front-end sample-and-hold circuit for both the residue circuit and the quantizer reduces power consumption and input-referred noise. By substantially matching the sampling characteristics of the two networks (i.e., that of the quantizer and that of the residue generator), aperture errors resulting from the parallel sampling (by the two networks) of high frequency input signals are greatly reduced.
In accordance with a first aspect, the invention involves an analog-to-digital converter having an input to receive an input signal; a quantizer, coupled to the input, to sample the input signal; and a residue generator, coupled to the quantizer and adapted to separately sample the input signal. The sampling characteristics of the residue generator are selected to substantially match sampling characteristics of the quantizer. The degree of matching of the sampling characteristics may be selected at least in part based upon an expected frequency range of the input signal.
According to a second aspect, the invention involves a method of sampling an input voltage including using a quantizer, sampling the input voltage; and using a residue generator operatively connected to receive an output from the quantizer, and having sampling characteristics substantially matching sampling characteristics of the quantizer, also sampling the input voltage. The sampling characteristics may be matched at least in part based upon an expected frequency range of the input signal.
According to a third aspect, the invention involves an analog-to-digital converter, having a residue generator and a quantizer, each having a sampling network connected to sample a same analog input signal and the sampling networks having substantially matched sampling characteristics. An output from the quantizer is operatively connected to provide an input to the residue generator, and the residue generator is configured and arranged to generate a residue signal from the quantizer output and samples from the residue generator sampling network. The matched sampling characteristics may include the bandwidths of the sampling networks and/or sampling timing. The quantizer may include a flash converter having a plurality of comparators, each having one input connected to a respective threshold voltage and one input connected to an output of the quantizer sampling network; and the quantizer sampling network may comprise a sample-and-hold circuit for each of said comparators.
According to a fourth aspect, the invention involves a pipelined analog-to-digital converter comprising a first stage, one or more intermediate stages each of which receives as input a residue signal output from an immediately preceding stage, a final stage which converts a residue output signal from a next-to-final stage into a corresponding digital signal and correction logic which receives each stage""s output and generates a corresponding digital word; and at least the first stage is an analog-to-digital converter as hereinabove described in connection with other aspects of the invention.
According to a still further aspect of the invention, an analog-to-digital converter having a residue generator may be provided with a quantizer; each of the residue generator and the quantizer may have a sampling network connected to sample a same analog input signal, with the sampling networks having substantially matched sampling characteristics such as bandwidth and timing. An output from the quantizer may be operatively connected to provide an input to the residue generator; and the residue generator may be being configured and arranged to generate a residue signal from the quantizer output and samples from the residue generator sampling network. Among the types of analog-to-digital converters which may employ this arrangement are (without limitation) pipeline converters, cyclic converters, pipeline sigma-delta converters, error-correcting successive approximation converters, and two-step converters.